The present invention relates to a data processing system which comprises a plurality of units, each of which is under pipeline control. The present invention specifically relates to a data processing system which utilizes microinstructions for controlling an arithmetic unit therein.
A conventional large scale data processing system typically processes an instruction by way of a plurality of partial processing operations. The system may comprise, for example, first to m.sup.th partial processing units where the number of partial processing operations is equal to m. Each partial processing operation is processed in a corresponding partial processing unit. The first partial processing operation is carried out in the first partial processing unit, and the second to m.sup.th partial processing operations are respectively carried out in second to m.sup.th partial processing units sequentially. Each partial processing unit is controlled in such a manner that it effects a corresponding partial processing operation of succeeding instructions in parallel and in overlapping relationship with every other partial processing unit and that each processing unit carries a corresponding partial processing operation in response to a synchronizing signal. These operations may include a decode processing operation (D operation) for decoding an instruction to be processed, and address modification processing operation (A operation) for calculating an operand address necessary for the execution of the instructions, a load processing operation (L operation) for reading out operands corresponding to the calculated operand addresses from memory, a transfer processing operation (T operation) for transferring the read out operands to an execution unit, and an execution processing operation (E operation) for executing an arithmetic or logical operation with the transferred operands. Each partial processing operation usually requires one machine cycle. If these five processing operations are processed sequentially for different instructions, the total execution time for successive instructions is equal to five machine cycles.
If these five partial processing operations are processed in parallel and in overlapping relationship for different instructions under pipeline control, the total execution time for successive instructions can be reduced to one machine cycle.
The above discussion of execution time is applicable only when each partial processing operation requires only one machine cycle; therefore, the total execution time of each instruction requires a minimum execution of five machine cycles. it is to be noted, however, that there are many instructions which require more than one machine cycle for one partial processing operation. One example of such instructions is an instruction for a decimal arithmetic operation. For such instructions, the execution time for successive instructions is reduced a considerable extent because a complete parallel processing operation cannot be maintained among different partial processing units, as will be explained below.
An instruction unit controls the partial processing units for respective partial processing operations D, A, L, T, and E, so that the units process corresponding partial processing operations in a pipeline mode. The E partial processing operation is carried out in an execution unit.
The instruction unit decodes successive instructions, calculates the operand addresses, reads out the operands designated by the calculated operand addresses, and transfers the read out operands to operand buffer registers to be stored therein.
An instruction for a decimal arithmetic operation requires more than one machine cycle for the execution of a partial processing operation because during execution in the execution unit an operand read out is required. The operands read out from memory in response to a request for an operand read out during execution of the instruction for a decimal arithmetic operation are also stored in the operand buffer registers.
The operand buffer registers are provided for use in common by the instruction unit and the execution unit in many data processing systems in order to reduce required hardware. The operands read out and stored in the operand buffer registers, in response to a request provided by the instruction unit, may be destroyed by the operands read out in response to a request provided by the execution unit, if the instruction being processed in the execution unit requires an operand or operands to be read out and partial processing operations for succeeding instructions are begun in parallel and in overlapping relationship.
In order to avoid operand destruction, a conventional data processing system prohibits process-instructions succeeding an instruction which requires that operands be read out in an E partial processing operation from being decoded, until the E partial processing operation for the instruction has been completed. An instruction which requires that an operand or operands be read out in an E operation is one of the so-called defeat overlap instructions. A defeat overlap instruction is an instruction which will invalidate partial operations of succeeding instructions, if the partial operations are processed in parallel and in overlapping relationship with the defeat overlap instruction. The defeat overlap instructions belong to the prior art and can be found in, for example, "IBM Maintenance Library: System/370 Model 168 Theory of Operations/Diagrams Manual (Volume 2) I unit, SY 22-6932-2" published by International Business Machines Corporation.
According to the prior art, when a defeat overlap instruction is decoded, succeeding instructions are prohibited from being decoded until the execution of the defeat overlap instruction is completed and the state in which the execution of succeeding instructions is prohibited is called a defeat overlap state. If the processing of succeeding instructions is begun in the instruction unit after the execution of the defeat overlap instruction has been completed, the succeeding instructions begin to be processed in the execution unit after an elapse of several machine cycles. Therefore, during these several machine cycles, the execution unit is idle (it does not execute any processing operation); during this time the processing of succeeding instructions cannot be completed. This results in an increase in the average execution time for successive instructions.